FIG. 2 shows a conventional output circuit.
The input terminal of a first inverter I1 constituted by a p-channel MOS transistor M1 and an n-channel MOS transistor M2 is connected to an input terminal 1, and the input terminal of a second inverter I2 constituted by an n-channel MOS transistor M3 and a p-channel MOS transistor M4 is connected to the input terminal 1. The sources of the p-channel MOS transistors M1 and M3 constituting the first and second inverters I1 and I2 are connected to a power source V.sub.DD, and the sources of the n-channel MOS transistors M2 and M4 are grounded. The output terminal of the second inverter I2 is connected to the base of an npn transistor Q1. The collector of the transistor Q1 is connected to the power source V.sub.DD through a resistor R1, and the emitter of the transistor Q1 is connected to an output terminal 2 through a diode D2.
The output terminal of the first inverter I1 is connected to the gates of a p-channel MOS transistor M5 and n-channel MOS transistors M6 and M7. The sources of the n-channel MOS transistors M6 and M7 are grounded, and a resistor R2 and a diode D1 are connected in series between the drains of the p-channel MOS transistor M5 and the n-channel MOS transistor M6. The base of an npn transistor Q2 is connected to the connection point between the diode D1 and the drain of the n-channel MOS transistor M6, and the base of the transistor Q2 is grounded through a resistor R3. The collector of the transistor Q2 is connected to the power source V.sub.DD and the source of the p-channel MOS transistor M5, and the emitter of the transistor Q2 is connected to the drain of the n-channel MOS transistor M7 and the base of an npn transistor Q3. The emitter of the transistor Q3 is grounded, and the collector thereof is connected to the output terminal I2. Therefore, the transistors Q1 and Q2 are totempole-connected to each other.
With the above arrangement, when the input terminal 1 is set at high level, the output from the inverter I1 goes to low level, the p-channel MOS transistor M5 is turned on and the n-channel MOS transistors M6 and M7 are turned off. Therefore, a base current is supplied to the base of the transistor Q2 through the p-channel MOS transistor M5, the resistor R2, and the diode D1, thereby turning on the transistor Q2. When the transistor Q2 is turned on, the transistor Q3 is turned on. At this time, since the transistor Q2 serves as an emitter follower, a large current is supplied to the transistor Q3.
FIG. 3 shows an output current when the output terminal 2 is set at low level. In FIG. 3, reference symbol I01 indicates a current flowing through the transistor Q3. As is apparent from FIG. 3, when tI output voltage Vout=0.5 V, an output current of A1=40 mA to 60 mA can be assured.
When the output voltage Vout=5 V, a large current of A2=700 to 800 mA is supplied to the transistor Q3. For this reason, when the transistor Q3 is turned on or off, the power source voltage V.sub.DD is varied by the large current, and an erroneous operation may be disadvantageously performed in other circuits (not shown) receiving the power source voltage V.sub.DD.